Gate driver circuits may be used to drive gates of power Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) or Insulated Gate Bipolar Transistors (IGBTs).
Gate drivers may be used in two channel devices, also known as dual channel devices. Such devices may drive power devices having both low and high sides. A common Integrated Circuit (IC) package, known as SO-8, may use a chip having eight connectors. Such connectors may also be known as pins.
Conventional gate drivers may have a problem with parastic inductances on the Printed Circuit Board (PCB). Such parasitic inductances may cause unwanted voltage excursions of the reference voltage both above and below the ground level.
Another problem may involve instability of the reference voltage for the input side of the gate driver. As this reference is noisy, the input levels may be characterized by unwanted toggling.
FIG. 1 illustrates propagation delay definitions for a gate driver circuit. Propagation delay, tpd, is an important characteristic for gate driver circuits. As shown in FIG. 1, a common definition of propagation delay involves a time difference between the initial time when an input signal rises above the 50% level and the subsequent time when the output signal rises above the 10% level. See tpd (L-LG) on to tpd (H-HG) on. A second propagation delay definition involves the time difference between the initial time when the input signal falls below the 50% level and the subsequent time when the output signal falls below the 90% level. See tpd (L-LG) off to tpd (H-HG) off.
FIG. 2 illustrates an exemplary related art gate driver 200 embodiment that uses input filters 208/209. Gate driver 200 includes a high input buffer 202, a low input buffer 203, a high undervoltage monitor 204, a low undervoltage monitor 205, a high output driver 206, and a low output driver 207. High input filter 208 and low input filter 209 are respectively coupled to the input sides of high input buffer 202 and low input buffer 203.
Microcontroller 240 includes a high input line 220 coupled to high input filter 208 and a low input line 230 coupled to low input buffer 209. The related art embodiment assumes that unwanted voltage excursions only occur for a limited period of time. Thus, related art devices may add respective input filter 208/209 before the input buffers 202/203 to prevent propagation of the unwanted voltage excursions. However, this solution has a significant drawback because it adds delay to both the H and L paths. Thus, there is a need for an improved gate driver circuit.